In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on\r\narray processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm,\r\nwere described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis\r\nresults showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115MHz operating\r\nfrequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support\r\n4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator\r\nimplemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance\r\nand reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current\r\ncommunications standards.
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